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resample_neon.h
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1/* Copyright (C) 2007-2008 Jean-Marc Valin
2 * Copyright (C) 2008 Thorvald Natvig
3 * Copyright (C) 2011 Texas Instruments
4 * author Jyri Sarha
5 */
11/*
12 Redistribution and use in source and binary forms, with or without
13 modification, are permitted provided that the following conditions
14 are met:
15
16 - Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18
19 - Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in the
21 documentation and/or other materials provided with the distribution.
22
23 - Neither the name of the Xiph.org Foundation nor the names of its
24 contributors may be used to endorse or promote products derived from
25 this software without specific prior written permission.
26
27 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR
31 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38*/
39
40#ifdef FIXED_POINT
41#if defined(__aarch64__)
42static inline int32_t saturate_32bit_to_16bit(int32_t a) {
43 int32_t ret;
44 asm ("fmov s0, %w[a]\n"
45 "sqxtn h0, s0\n"
46 "sxtl v0.4s, v0.4h\n"
47 "fmov %w[ret], s0\n"
48 : [ret] "=r" (ret)
49 : [a] "r" (a)
50 : "v0" );
51 return ret;
52}
53#elif defined(__thumb2__)
54static inline int32_t saturate_32bit_to_16bit(int32_t a) {
55 int32_t ret;
56 asm ("ssat %[ret], #16, %[a]"
57 : [ret] "=r" (ret)
58 : [a] "r" (a)
59 : );
60 return ret;
61}
62#else
63static inline int32_t saturate_32bit_to_16bit(int32_t a) {
64 int32_t ret;
65 asm ("vmov.s32 d0[0], %[a]\n"
66 "vqmovn.s32 d0, q0\n"
67 "vmov.s16 %[ret], d0[0]\n"
68 : [ret] "=r" (ret)
69 : [a] "r" (a)
70 : "q0");
71 return ret;
72}
73#endif
74#undef WORD2INT
75#define WORD2INT(x) (saturate_32bit_to_16bit(x))
76
77#define OVERRIDE_INNER_PRODUCT_SINGLE
78/* Only works when len % 4 == 0 and len >= 4 */
79#if defined(__aarch64__)
80static inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
81{
82 int32_t ret;
83 uint32_t remainder = len % 16;
84 len = len - remainder;
85
86 asm volatile (" cmp %w[len], #0\n"
87 " b.ne 1f\n"
88 " ld1 {v16.4h}, [%[b]], #8\n"
89 " ld1 {v20.4h}, [%[a]], #8\n"
90 " subs %w[remainder], %w[remainder], #4\n"
91 " smull v0.4s, v16.4h, v20.4h\n"
92 " b.ne 4f\n"
93 " b 5f\n"
94 "1:"
95 " ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [%[b]], #32\n"
96 " ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [%[a]], #32\n"
97 " subs %w[len], %w[len], #16\n"
98 " smull v0.4s, v16.4h, v20.4h\n"
99 " smlal v0.4s, v17.4h, v21.4h\n"
100 " smlal v0.4s, v18.4h, v22.4h\n"
101 " smlal v0.4s, v19.4h, v23.4h\n"
102 " b.eq 3f\n"
103 "2:"
104 " ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [%[b]], #32\n"
105 " ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [%[a]], #32\n"
106 " subs %w[len], %w[len], #16\n"
107 " smlal v0.4s, v16.4h, v20.4h\n"
108 " smlal v0.4s, v17.4h, v21.4h\n"
109 " smlal v0.4s, v18.4h, v22.4h\n"
110 " smlal v0.4s, v19.4h, v23.4h\n"
111 " b.ne 2b\n"
112 "3:"
113 " cmp %w[remainder], #0\n"
114 " b.eq 5f\n"
115 "4:"
116 " ld1 {v18.4h}, [%[b]], #8\n"
117 " ld1 {v22.4h}, [%[a]], #8\n"
118 " subs %w[remainder], %w[remainder], #4\n"
119 " smlal v0.4s, v18.4h, v22.4h\n"
120 " b.ne 4b\n"
121 "5:"
122 " saddlv d0, v0.4s\n"
123 " sqxtn s0, d0\n"
124 " sqrshrn h0, s0, #15\n"
125 " sxtl v0.4s, v0.4h\n"
126 " fmov %w[ret], s0\n"
127 : [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
128 [len] "+r" (len), [remainder] "+r" (remainder)
129 :
130 : "cc", "v0",
131 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23");
132 return ret;
133}
134#else
135static inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
136{
137 int32_t ret;
138 uint32_t remainder = len % 16;
139 len = len - remainder;
140
141 asm volatile (" cmp %[len], #0\n"
142 " bne 1f\n"
143 " vld1.16 {d16}, [%[b]]!\n"
144 " vld1.16 {d20}, [%[a]]!\n"
145 " subs %[remainder], %[remainder], #4\n"
146 " vmull.s16 q0, d16, d20\n"
147 " beq 5f\n"
148 " b 4f\n"
149 "1:"
150 " vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
151 " vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
152 " subs %[len], %[len], #16\n"
153 " vmull.s16 q0, d16, d20\n"
154 " vmlal.s16 q0, d17, d21\n"
155 " vmlal.s16 q0, d18, d22\n"
156 " vmlal.s16 q0, d19, d23\n"
157 " beq 3f\n"
158 "2:"
159 " vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
160 " vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
161 " subs %[len], %[len], #16\n"
162 " vmlal.s16 q0, d16, d20\n"
163 " vmlal.s16 q0, d17, d21\n"
164 " vmlal.s16 q0, d18, d22\n"
165 " vmlal.s16 q0, d19, d23\n"
166 " bne 2b\n"
167 "3:"
168 " cmp %[remainder], #0\n"
169 " beq 5f\n"
170 "4:"
171 " vld1.16 {d16}, [%[b]]!\n"
172 " vld1.16 {d20}, [%[a]]!\n"
173 " subs %[remainder], %[remainder], #4\n"
174 " vmlal.s16 q0, d16, d20\n"
175 " bne 4b\n"
176 "5:"
177 " vaddl.s32 q0, d0, d1\n"
178 " vadd.s64 d0, d0, d1\n"
179 " vqmovn.s64 d0, q0\n"
180 " vqrshrn.s32 d0, q0, #15\n"
181 " vmov.s16 %[ret], d0[0]\n"
182 : [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
183 [len] "+r" (len), [remainder] "+r" (remainder)
184 :
185 : "cc", "q0",
186 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23");
187
188 return ret;
189}
190#endif // !defined(__aarch64__)
191
192#elif defined(FLOATING_POINT)
193#if defined(__aarch64__)
194static inline int32_t saturate_float_to_16bit(float a) {
195 int32_t ret;
196 asm ("fcvtas s1, %s[a]\n"
197 "sqxtn h1, s1\n"
198 "sxtl v1.4s, v1.4h\n"
199 "fmov %w[ret], s1\n"
200 : [ret] "=r" (ret)
201 : [a] "w" (a)
202 : "v1");
203 return ret;
204}
205#else
206static inline int32_t saturate_float_to_16bit(float a) {
207 int32_t ret;
208 asm ("vmov.f32 d0[0], %[a]\n"
209 "vcvt.s32.f32 d0, d0, #15\n"
210 "vqrshrn.s32 d0, q0, #15\n"
211 "vmov.s16 %[ret], d0[0]\n"
212 : [ret] "=r" (ret)
213 : [a] "r" (a)
214 : "q0");
215 return ret;
216}
217#endif
218
219#undef WORD2INT
220#define WORD2INT(x) (saturate_float_to_16bit(x))
221
222#define OVERRIDE_INNER_PRODUCT_SINGLE
223/* Only works when len % 4 == 0 and len >= 4 */
224#if defined(__aarch64__)
225static inline float inner_product_single(const float *a, const float *b, unsigned int len)
226{
227 float ret;
228 uint32_t remainder = len % 16;
229 len = len - remainder;
230
231 asm volatile (" cmp %w[len], #0\n"
232 " b.ne 1f\n"
233 " ld1 {v16.4s}, [%[b]], #16\n"
234 " ld1 {v20.4s}, [%[a]], #16\n"
235 " subs %w[remainder], %w[remainder], #4\n"
236 " fmul v1.4s, v16.4s, v20.4s\n"
237 " b.ne 4f\n"
238 " b 5f\n"
239 "1:"
240 " ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[b]], #64\n"
241 " ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [%[a]], #64\n"
242 " subs %w[len], %w[len], #16\n"
243 " fmul v1.4s, v16.4s, v20.4s\n"
244 " fmul v2.4s, v17.4s, v21.4s\n"
245 " fmul v3.4s, v18.4s, v22.4s\n"
246 " fmul v4.4s, v19.4s, v23.4s\n"
247 " b.eq 3f\n"
248 "2:"
249 " ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[b]], #64\n"
250 " ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [%[a]], #64\n"
251 " subs %w[len], %w[len], #16\n"
252 " fmla v1.4s, v16.4s, v20.4s\n"
253 " fmla v2.4s, v17.4s, v21.4s\n"
254 " fmla v3.4s, v18.4s, v22.4s\n"
255 " fmla v4.4s, v19.4s, v23.4s\n"
256 " b.ne 2b\n"
257 "3:"
258 " fadd v16.4s, v1.4s, v2.4s\n"
259 " fadd v17.4s, v3.4s, v4.4s\n"
260 " cmp %w[remainder], #0\n"
261 " fadd v1.4s, v16.4s, v17.4s\n"
262 " b.eq 5f\n"
263 "4:"
264 " ld1 {v18.4s}, [%[b]], #16\n"
265 " ld1 {v22.4s}, [%[a]], #16\n"
266 " subs %w[remainder], %w[remainder], #4\n"
267 " fmla v1.4s, v18.4s, v22.4s\n"
268 " b.ne 4b\n"
269 "5:"
270 " faddp v1.4s, v1.4s, v1.4s\n"
271 " faddp %[ret].4s, v1.4s, v1.4s\n"
272 : [ret] "=w" (ret), [a] "+r" (a), [b] "+r" (b),
273 [len] "+r" (len), [remainder] "+r" (remainder)
274 :
275 : "cc", "v1", "v2", "v3", "v4",
276 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23");
277 return ret;
278}
279#else
280static inline float inner_product_single(const float *a, const float *b, unsigned int len)
281{
282 float ret;
283 uint32_t remainder = len % 16;
284 len = len - remainder;
285
286 asm volatile (" cmp %[len], #0\n"
287 " bne 1f\n"
288 " vld1.32 {q4}, [%[b]]!\n"
289 " vld1.32 {q8}, [%[a]]!\n"
290 " subs %[remainder], %[remainder], #4\n"
291 " vmul.f32 q0, q4, q8\n"
292 " bne 4f\n"
293 " b 5f\n"
294 "1:"
295 " vld1.32 {q4, q5}, [%[b]]!\n"
296 " vld1.32 {q8, q9}, [%[a]]!\n"
297 " vld1.32 {q6, q7}, [%[b]]!\n"
298 " vld1.32 {q10, q11}, [%[a]]!\n"
299 " subs %[len], %[len], #16\n"
300 " vmul.f32 q0, q4, q8\n"
301 " vmul.f32 q1, q5, q9\n"
302 " vmul.f32 q2, q6, q10\n"
303 " vmul.f32 q3, q7, q11\n"
304 " beq 3f\n"
305 "2:"
306 " vld1.32 {q4, q5}, [%[b]]!\n"
307 " vld1.32 {q8, q9}, [%[a]]!\n"
308 " vld1.32 {q6, q7}, [%[b]]!\n"
309 " vld1.32 {q10, q11}, [%[a]]!\n"
310 " subs %[len], %[len], #16\n"
311 " vmla.f32 q0, q4, q8\n"
312 " vmla.f32 q1, q5, q9\n"
313 " vmla.f32 q2, q6, q10\n"
314 " vmla.f32 q3, q7, q11\n"
315 " bne 2b\n"
316 "3:"
317 " vadd.f32 q4, q0, q1\n"
318 " vadd.f32 q5, q2, q3\n"
319 " cmp %[remainder], #0\n"
320 " vadd.f32 q0, q4, q5\n"
321 " beq 5f\n"
322 "4:"
323 " vld1.32 {q6}, [%[b]]!\n"
324 " vld1.32 {q10}, [%[a]]!\n"
325 " subs %[remainder], %[remainder], #4\n"
326 " vmla.f32 q0, q6, q10\n"
327 " bne 4b\n"
328 "5:"
329 " vadd.f32 d0, d0, d1\n"
330 " vpadd.f32 d0, d0, d0\n"
331 " vmov.f32 %[ret], d0[0]\n"
332 : [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
333 [len] "+l" (len), [remainder] "+l" (remainder)
334 :
335 : "cc", "q0", "q1", "q2", "q3",
336 "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11");
337 return ret;
338}
339#endif // defined(__aarch64__)
340#endif